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Pоssibly useful infоrmаtiоn: Device Fаmily: MAX 10 (DA/DF/DC/SA/SC) Device: 10M02SCU169C8G -- VHDL Syntаx Examplelibrary ieee; use ieee.std_logic_1164.all;entity NAND2a is port( A,B: in bit; C: out bit);end NAND2a;architecture behavior of NAND2a issignal COut: bit;begin ...end behavior; Problem Description Design, construct, and demonstrate a circuit that meets the following specifications to output a sequence of bits (displayed using your DAD) represented by the infinite sequence of octal numbers 3, 7, 7, 3, 7, 7, 3, 7, …, advancing on the rising edge of a signal called CLK. This is the sequence when input Go(H) is true; when Go is false, the sequence should pause, i.e., the sequence should not continue the sequence until GO is again true. Inputs: CLK, Go(H), Start(L) Outputs: YJ(H), Sp(L) The Sp output should be true ONLY when the sequence is on the second 7 (1112) and Go is true. Whenever Start is true, the sequence must immediately restart at the second 7. Notes: The sequence repeats forever. Be very careful to read the sequence correctly and note that when Go is false, the sequence is paused. Part 1 Show ALL work on your scratch paper. You will not get credit if the below work is not shown. Make a next-state truth for this problem. Use the usual counting order for the table. For the outputs YJ, Y0 should be the least significant bit. Use whatever flip-flop(s) that you prefer; I suggest T-FF(s). Draw a functional block diagram for this problem. Draw the switch and LED circuit diagrams. The CLK signal will be supplied by your DAD. Also use your DAD for the Y outputs. Use your DAD Waveform’s StaticIO for both. Determine equations for all of the necessary signals. Design the circuit in Quartus. Simulate the design in Quartus, as specified below: Group the outputs YJ, such that Y0 is the least significant bit. Display the Y outputs with the radix in octal (i.e., base 8). Make Start true and Go true for exactly 3 clock cycles. Then make Start false and Go true for exactly four clock cycles. Then make Start false and Go false for exactly four clock cycles. Then make Start true and Go false for exactly three clock cycles. Part 2 Program your PLD and build the circuit on your breadboard. Use NO 74'xxx chips. See below for specifications on your inputs and outputs. Use your DAD for CLK (using your DAD Waveform’s StaticIO). Do NOT build physical switch circuits for CLK. Replacing your DAD with physical switch circuits is okay, but will result in a significant point reduction. Build a physical switch circuit for Go(H) and Start (L), i.e., do NOT use your DAD. Replacing your physical switch circuit with your DAD is okay, but will result in a significant point reduction. Make a legend for Go(H) and Start(L), indicating the true positions, as you did for switches in lab. Use your DAD for the octal output sequence YJ (where J is the bit position 0, 1, …). These bits must be displayed using your DAD Waveform’s StaticIO; the least significant bit (Y0) must be on the right with the other bits in appropriate positions immediately to the left of Y0. Do NOT build physical LED circuits for YJ. Replacing your DAD with physical LED circuits is okay, but will result in a significant point reduction. Build a physical LED circuit for Sp(L), i.e., do NOT use your DAD. Replacing your physical LED circuits with your DAD is okay, but will result in a significant point reduction. The physical LED should be illuminated when Sp(L) is true. Make a legend for the LED to indicate which LED corresponds to Sp(L), as you did in lab. Other than the above, build the circuit using only your PLD, either of your two breadboards, wires, switches, LEDs, and resistors (i.e., as specified above). No physical 74xxx parts are allowed. Verify to yourself that your circuit is functioning properly. Archive this Quartus project and submit it as part of this practical, as described below. Use CamScanner (or equivalent), as described below, to make a pdf file to submit as part of this practical. Be sure that the scan is clear on your phone before uploading. Demonstration You will show your Quartus simulation, as described above. You will demonstrate the proper functioning of your physical circuit, following the PI's instructions with inputs. You will have only ONE chance to demo your work. If you think you are ready, read the question again to be sure that you completed ALL parts of this practical. Do not ask us for any feedback on your design. Be prepared to show (and re-run) your simulation and to run your design, as instructed, by a PI or Dr. Schwartz. If ready prior to the end of the practical, use Zoom's chat to tell your PI that you are ready by sending READY. You will NOT be told anything about how you did, but grades will be posted ASAP. Submissions You MUST complete the two file uploads (see below) before the end of your practical. If you have not already done so, when there are five minutes remaining in your practical, you should stop working and start this process. You must archive your Quartus design and upload it (in the next problem). In the last problem, you must upload a single pdf file (use CamScanner or equivalent) containing a clear picture of your breadboard that shows your circuit (as well as switch and LED legends) and also contains clear pictures of your scratch paper, showing the next state truth table and any equations that were derived. Failure to upload these files before the end of the practical will result in a grade of zero.