Prоblem 1: Shоrt Questiоns (24 pts) 1.1 Pleаse select True or Fаlse for the following stаtements. (8 pts) (True / False) a. DIBL effect leads to lower device leakage. (True / False) b. A 7nm FinFET transistor has its gate length at 7nm. (True / False) c. At the same length, metal-1 has a lower resistance and capacitance than metal-3. (True / False) d. Hold time violations are easier to fix than setup time violations after a chip is fabricated. (True / False) e. Fin width (FinFET) is a design parameter that a circuit designer decides as she wishes. (True / False) f. DRC rules are defined by the EDA tool vendors, such as Cadence. (True / False) g. Carry out bit is often on the critical path of a 1-bit full adder. (True / False) h. Clock skew is the difference in arrival times between the launch flip-flop clock edge and the capture flip-flop clock edge. [Write down your answers on your solution papers. No explanation is needed.]
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