Which оf the fоllоwing best describes а "bill of mаteriаls"?
Textbооk Exercises 2.43, 2.44, 4.1, 4.2, 4.5, аnd 4.8 - Detаiled wоrk PDFUploаd ONE readable PDF containing all six labeled work groups. Include handwritten derivations, schematics, complete SystemVerilog code, and any simulation screenshots in this one file. Confirm orientation and legibility before submitting.Grading rubric - 30 points Final-answer checks: 24 points, automatically graded. There are twelve 2-point questions. Each item is all-or-nothing at its displayed value. Detailed work: 6 points, manually graded from the final PDF upload. Each of the six work groups is worth 1 point. The automatic score shown immediately after submission is provisional until the PDF is reviewed. Criterion for each work groupPointsWhat earns credit Reasoning and method0.50Show the timing paths, algebra, truth-table reasoning, or HDL design steps. A meaningful but incomplete attempt earns 0.25; an answer alone earns 0. Required representation0.25Include the labeled path diagram, simplified schematic, truth table, or complete SystemVerilog module requested for that group. Verification and clear labels0.25Label the textbook exercise and signals, include units where appropriate, and perform the requested hand checks or simulation evidence. Equivalent correct logic and synthesizable SystemVerilog earn work credit. Readable reasoning can earn work credit even if the final answer is wrong. A PDF containing only final answers earns 0/6 for detailed work.Required work groups Group 1 - Exercise 2.43 (4 auto points + 1 work point)Redraw Figure 2.83, label every gate and every input-to-output path, calculate both delays for each distinct path, and mark the propagation-critical and contamination-critical paths. Group 2 - Exercise 2.44 (4 auto points + 1 work point)Redraw Figure 2.84, label the NAND/NOR/AND gates, calculate both delays for each distinct path, and mark the longest and shortest paths. Group 3 - Exercise 4.1 (4 auto points + 1 work point)Simplify both HDL equations step by step and sketch the minimum-gate schematic for outputs y and z. Verify at least two contrasting input cases. Group 4 - Exercise 4.2 (4 auto points + 1 work point)Trace the priority order, build a complete or logically compressed input/output table, derive simplified equations for y[1] and y[0], and sketch a labeled implementation. Check at least three cases with multiple asserted inputs. Group 5 - Exercise 4.5 (4 auto points + 1 work point)Create the eight-row truth table, derive a minimized minority equation, and write a complete synthesizable SystemVerilog module named minority. Verify at least three contrasting cases. Group 6 - Exercise 4.8 (4 auto points + 1 work point)Write a complete synthesizable mux8 module, show the select-to-data mapping, and verify selections 000, 101, and 111. Include either a compact testbench/waveform screenshot or clear hand traces.
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