Imagine in the PennSim simulator line 3 (address 0x321F) was highlighted yellow (line of code to be executed next). If we hit:    Step the next line highlighted would be [1]    If instead we hit Next the next line highlighted would be [2] If the current highlighted line was line 7 (address 0x3222) and we hit Next the next line highlighted would be [3]

Simulate different scenarios in your head, but in all scenarios assume condition check is eventually false Then give the best answer to the following: Shape A is [1] Shape B is [2] Shape C is [3] Shape E is [4]

To perform an LDI instruction the processor first [off_ext] and [addr_form] this result is [first_op].  The data [op] is then [2nd_op], and data returned is [final]

At what 4-digit hex address is the label LOOP defined [1] What offset (answer as a decimal number) would be encoded into the BRnp instruction [2] True/False: (simply type true or false in the box) the program would not work if line 29 was: RESULT  .BLKW 1                  [3]  

When a BRnz instruction is executed, the branch will be taken [1] The BRnz branch will be taken if the last value written to a register was [2] If one leaves the flag specifiers off a BRx instruction  (i.e. just a BR instruction) the [3]  

The destination of this instruction is (type a specific register (i.e R0) or type memory if it is memory) [1] The address in memory being accessed is (enter 4-digit hex number) [2]

Complete the drop downs to implement blocks A and B of this flowchart in most logical way                  [1][2][3]                  [4][5][6]                  [7][8]

Consider the operations occurring in block C Remark on the order of operations for block C

Implement in optimal manner TEST               [1] R1, [2]                            [3] [4] R0_IS_5        ;  code if R0 = 5                            …                            [5][6] R0_ISNT_5 ; code if R0 

Use your LC-3 Programmer’s Reference and decode the following instruction: 1011 0110 0000 0111 What type of instruction is this? [instr] The source data for this instruction comes from [orig] Given the state of the processor show (after PC already incremented) One of the addresses in memory this instruction accesses is [addr] The CC (NZP) after this instructions executes are [CC]