Which of the following assertions correctly verify a synchro…
Which of the following assertions correctly verify a synchronous reset, where the following register’s output out is all 0s in the next cycle after reset is asserted? Select all that apply. Assume a 200 MHz clock. module register #( parameter WIDTH ) ( input logic clk, input logic rst, input logic en, input logic [WIDTH-1:0] in, output logic [WIDTH-1:0] out );
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What is the minimum number of tests (directed or random) that would be required to achieve 100% coverage for the following cover group? module add #( parameter WIDTH ) ( input logic [WIDTH-1:0] in0, in1, input logic carry_in, output logic [WIDTH-1:0] sum, output logic carry_out ); covergroup cg @(posedge clk); cin : coverpoint carry_in; cout : coverpoint carry_out; in0_cp : coverpoint in0 {option.auto_bin_max = 4;} in1_cp : coverpoint in1 {option.auto_bin_max = 4;} in0_cross_in1 : cross in0_cp, in1_cp; endgroup
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