A state transition diagram for a finite state machine is given. The clock input is 100 MHz. Suppose the FSM is currently in state S3 and the inputs are AB = 01.  What will the state be after the next clock edge?  What will the output be?

Given:  The size of a memory array is 128 x 8.  How many bits does the WD line have?

A circuit that implements a finite state machine is given. The clock input is 100 MHz. Suppose the current state of the FSM is S1:0 = 10 and the inputs are AB = 00.  What will the state be after the next clock edge?  What will the output Y1 be?

A state transition diagram for a finite state machine is given. The clock input is 100 MHz. Suppose the FSM is currently in state S0 and the inputs are AB = 10.  What will the state be after the next clock edge?  What will the output be?

A timing diagram is given for a 3-bit counter. What is the value of the Q0 output at time = 65 ns?  Assume the delay from inputs changing to outputs changing is negligible.

Select the answer that best completes this sentence: If the input to a flip-flop changes outside the aperture time, then the flip-flop _______________.

A circuit that implements a finite state machine is given. The clock input is 100 MHz. Suppose the current state of the FSM is S1:0 = 11 and the inputs are AB = 11.  What will the state be after the next clock edge?  What will the output Y2 be?

Q6-B-8 points    In a certain state, all license plates consist of from 4 to 6 symbols chosen from the 26 letters together with the ten digits (0-9) a) How many license plates are possible, repetition allowed ? b) What is the probability that license plates chosen at random have at least one repeated symbol?

Select the statement that best describes DRAM.

Q7-C-8 points A group of 12 students is available. A team of 6 students is to be selected and then arranged in a line for a photo. In how many ways can this be done?