Given a mutex lock m, and a conditional variable c, threads T1, T2, and T3 execute the following actions in order of occurrence: T2 executes mutex-lock(m). T3 executes mutex-lock(m). T2  executes cond-wait(c, m). T1 executes mutex-lock(m) T3 executes cond-signal(c) T3 executes mutex-unlock(m)   For each of the following three questions, write down the state of the two waiting queues after the indicated number of steps has elapsed.    For the mutex variable mm, write your answers as a comma-separated list with the first entry being the thread that currently has the lock. For example, if T1T1 has the lock and T2T2 is waiting for the lock, you should answer “T1, T2”. If the queue is empty, simply write “N/A”. For the conditional variable cc, write a comma-separated list of threads waiting in order that they arrived. For instance, if T1T1 and T2T2 are waiting for mutex lock mm, you should answer “T1 m, T2 m.” If the queue is empty, simply write “N/A”.

What of the size (in bits) of the index?

Suppose we want to implement the generic LC-2200 Instruction LW DR, offset20(BaseR) on a pipeline. According to the pipelined processor architecture described below, what are the minimum contents that must be placed in each pipeline buffer to support this instruction?

Listed below are the cache parameters that describe the cache layout for a byte-addressable memory system: 2 way set associative 32 bit address block size of 32 words word size of 4 bytes total cache size of 64K words (256 KB) Use these parameters to evaluate how this cache will interpret an address and the sizes of each part of the address. (Also, use 1 KB = 1024 B = 2^10 B) Remember the address is interpreted by the cache using the following format: tag | index | offset. Given the following cache address, answer the following. Cache address = 01010101 10101010 00110011 11001100 10011001 11111111 01100110 11101110

Write any assumptions you may have made below.

You are given a 4-way set associative cache. Each cache set has four cache entries, valid bits, and “Least Recently Used (LRU)” bits, which holds a sequence of caches ordered based on how recently they were used. For example, an entry of  C1 -> C2 -> C3 -> C0 indicates C0 as the least recently used cache entry. In the tables below, an entry denotes the memory address whose data is stored at that location, not the data itself. Additionally, assume the entry in the “Valid” column for an index is the value of the valid bit for each entry at that index. An “O” means each entry in the index is valid, and an “X” means each entry in the index is invalid.   Given the current state of the cache below, what will happen if the CPU accesses the memory location of 22? Assume that location 22 has been previously referenced in the cache.

When an application first starts up, it tends to experience some latency due to [q1] misses which could be somewhat reduced by [q2] the [q3].

Consider the following 5-stage pipeline with the provided per stage delay. What is the maximum frequency this pipeline can be clocked at in MHz? (1 MHz = 106 Hz; 1 ns = 10-9 s; 1 Hz = 1 clock cycle/s) Give your answer as a whole number without units. [q1]   Sean decides to modify this pipeline by combining the ID/RR and EX stages. The new per stage delay will be the sum of the per stage delays of the 2 combined stages. What will the pipeline’s new frequency be in MHz? Give your answer as a whole number in MHz without units. [q2]

What is the index?

What is the offset (in binary) of the given cache address?