A car is moving at a constant velocity of 3 m/s. What is its acceleration between t = 0  and t = 3 s time?

Displacement vector A →  is directed to the west and has magnitude 3.36 km. A second displacement vector B → is also directed to the west and has magnitude 9.14 km. What is the magnitude of A → + B → ?

A ball is fired by a cannon from the top of a cliff as shown in the figure below. Which of the paths would the cannonball most closely follow?Screen Shot 2021-09-10 at 7.11.07 AM(1).png  

Consider a 32-bit hexadecimal number stored in memory as follows:   Address Value 100 2A 101 C2 102 08 103 1B   1. (2 points) If the machine is big endian and uses 2’s complement representation for integers, write the 32-bit integer number stored at address 100 (you may write the number in hex). 2.  (2 points) If the machine is big endian and the number is an IEEE single-precision floating point value, is the number positive or negative? 3. (4 points)If the machine is big endian and the number is an IEEE single-precision floating point value, determine the decimal equivalent of the number stored at address 100 (you may leave your answer in scientific notation form, as a number times a power of two).

Perform the following binary divisions, assuming unsigned integers: 11111101 ÷ 1011

Suppose we have just found yet another representation for floating point numbers. Using this representation, a 12-bit floating point number has 1 bit for the sign of the number, 4 bits for the exponent and 7 bits for the mantissa, which is normalized as in the Simple Model so that the first digit to the right of the radix points must be a 1.  Numbers in the exponent are in signed 2’s complement representation.  No bias is used and there are no implied bits.  Show the representation for the smallest positive number this machine can represent using the following format.  What decimal number does this equate to?              

Write a MIPS program that always checks the bit 0 of a memory data at address 0x0BF81234. If it is equal to one add nth  and (n+1)th elements of an array and store it to memory address 0x0BF85678 . Suppose $t0  contains the address of the 0th element of an array of 32-bit data and $t1 = n.  

Examine the function prototype and MIPS implementation below.   // sets *value = (*value) * 2^pow using shifting instructions int multMemPow2(int *value, unsigned int pow);   multMemPow2:   1 lw $v0, 0($a0) # load value 2 loop: beq $a1, $0, exit # exit condition 3 sll $v0, $v0, 1 # multiply by 2 4 addi $a1, $a1, -1 # decrement counter 5 sw $v0, 0($a0) # store result 6 j loop 7 exit: jr $ra   We are using a 5 – stage MIPS pipelined datapath with separate I$ and D$ that can read and write to registers in a single cycle. Assume no other optimizations (no forwarding, no branch prediction, etc.). The default behavior is to stall when necessary. Branch checking is done during the Execute stage.   For parts (1)‐(3), let pow=1. When we ask for clock cycles to execute multMemPow2, we mean from the instruction fetch of lw up to and including the write back of jr.   How many instructions are executed in multMemPow2?

Consider each of the following sets of instructions. Decide the minimum number of stalls needed in each case with and without forwarding. Assume the five stage MIPS pipeline discussed in class and that equality for branches are checked at the Decode stage. Assume delayed branching.  Number of stalls required?   Without forwarding With forwarding addiu $t1, $t0, 5 addu $t4, $t3, $t1 addu $t0, $t3, $t0     lw $t0, 4($s0) addu $t1, $t2, $t3 beq t0, t1, Done addu $t5, $t5, $s5       lw t1, 0($s0) sw t1, 0($s1)     addu $t0, $s0, $t1 lw $t1 8($t0)    

In an attempt to improve cache performance, you try a new strategy. You think that because your L1 cache has a hit rate of 90%, you could improve the AMAT by randomly going straight to memory 10% of the time instead of first checking the L1 cache. Assuming the cache has a hit time of 5 cycles, and memory has an access time of 100 cycles, calculate the AMAT for this “improved” system.      Average Memory Access Time =                                                                               cycles