Assume a classic five-stage single-pipeline microarchitectur…
Assume a classic five-stage single-pipeline microarchitecture (fetch, decode, execute, memory, write back). Also, assume (1) one branch delay slot (originally with an NOP instruction in it) (2) adequate hardware resources, and (3) branch calculation always taken in the Decode stage. Also, the MULTI instruction is fully pipelined and takes two execution cycles. For the following loop, Loop: LW R3, 0(R6) ; load word at memory address [R6] + 0 to R3 LW R1, 0(R3) ; load word at memory address [R3] + 0 to R1 MULTI R1, R1, #6 ; Multiplying [R1] by 6 and put in R1 SW R1, 0(R3) ; Store [R1] at memory address [R3] + 0 ADDI R6, R6, #4 BNEQ R6, R4, Loop a. How many pipeline stalls are there for one loop if there is no forwarding scheme implemented? Show the details. b. Assuming perfect pipeline, unroll the loop two times and reschedule the instructions to reduce pipeline stalls. Show the details.
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