A timing diagram is given for a 3-bit counter. What is the value of the Q0 output at time = 115 ns?  Assume the delay from inputs changing to outputs changing is negligible.

True or False: multipliers generally use more power than adders

Given: 01000001010010000000000000000000 is an IEEE-754 single precision floating-point number.  What are the first 6 bits of the mantissa (ex: “0.00000”)?

A state transition diagram for a finite state machine is given. The clock input is 100 MHz. Suppose the FSM is currently in state S3 and the inputs are AB = 11.  What will the state be after the next clock edge?  What will the output be?

Given: 01000000101100000000000000000000 is an IEEE-754 single precision floating-point number.  What are the first 6 bits of the mantissa (ex: “0.00000”)?

Given:  The size of a memory array is 4K x 18.  How many bits does the RD line have?

A state transition diagram for a finite state machine is given. The clock input is 100 MHz. Suppose the FSM begins in state S0 and AB = 00.  One second later AB = 10, one second after that AB = 11, one second after that AB = 01.  What state is the FSM in at that point?    

A timing diagram is given for a 3-bit counter. What is the value of the count (Q2:0) at time = 145 ns?  Assume the delay from inputs changing to outputs changing is negligible.  Give your answer in decimal (ex: “2”, “7”)

A state transition table for a finite state machine is given. The clock input is 100 MHz. Suppose the FSM is currently in state S3 and the inputs are AB = 00.  What will the state be after the next clock edge?  What will the output be?

Given: A finite state machine has 16 states.  What is the minimum number of flip-flops required if binary encoding is used to encode the state?