Transistor Sizing and Propagation Delay Given the transistor-level circuit in the figure, assume unit resistance and unit capacitance of minimum-sized inverter are

What is the critical path of the circuit?

Size the gates on the critical path from Question 12 to minimize the delay. Leave the first stage gate to be minimum-sized. There is no need to further compute the transistor sizes. Assume that branch effort b (or path effort h) is converged after first iteration (no need check, no need to continue the iterations). Input the final answer in the box below and upload your work on Gradescope to get any credit.

Find a false statement about transistor scaling. Assume scaling factor to be .  

Assuming all gates are minimum sized, what is the propagation delay from a to z, , in terms of ? Input the final answer in the box below and upload your work on Gradescope to get any credit.

Assuming all gates are minimum sized, what is the propagation delay from a to x, , in terms of ? Input the final answer in the box below and upload your work on Gradescope to get any credit.

Find a true statement about combinational logic design.

In Episode 6, a character’s “Affect” is used to judge their guilt. In psychology, “Affect” refers to:

The “Miranda Warning” must be given when a suspect is in:

The “Dual-Process Model” of juror decision-making suggests jurors use: