In the following ladder logic diagram, the subroutine is executed ____.

When RET instruction is executed, the processor jumps from the ____.

If the accumulated register on an Allen-Bradley SLC 500 PLC non-retentive timer on-delay (TON) is equal to the preset register, which of the following statement is correct?

What are the registers used for each Allen-Bradley SLC 500 PLC timer?

The counter done bit for count up instruction C5:0 is addressed as ______________________________.

When you energize JMP instructions, all outputs in the JMP zone will ____.

For the following ladder logic diagram displayed, the green pilot light (G-PLT) will turn on when ____.

In a subtract instruction, Source______________________________ is deducted from Source ______________________________.

In the divide instruction, the content of Source ______________________________ is divided by the content of Source ______________________________.

Which counter down (CTD) flag bit is energized when input to CTD is on?