Fill in the following code for the behavioral architecture o…
Fill in the following code for the behavioral architecture of an ALU using the numeric standard library. Write the correct code for each region as specified by the comments around regions. library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity example is generic (width : positive := 4); –width will ALWAYS be even port ( in1 : in std_logic_vector(width-1 downto 0); in2 : in std_logic_vector(width-1 downto 0); sel : in std_logic_vector(1 downto 0); out1 : out std_logic_vector(width-1 downto 0); out2 : out std_logic_vector(width-1 downto 0); overflow : out std_logic );end example;architecture BHV of example isbegin — REGION 1: Write what goes in the process list below — process( ) –variables list – no need to write anything here variable temp_add : unsigned(width downto 0); variable temp_mult : unsigned(2*width-1 downto 0); begin — REGION 2: Initialize any signals below — case sel is –for region 3 compare: if in1 greater than in2 subtract in1 by in2 –if not add and set the overflow bit as width. set both outputs in out1 when “00” => — REGION 3: Write code below — –for region 4 compare: if in1 is equal to “1111” then ‘and’ in1 and in2 and set the result to out1. –Then elsif in2 is equal to “0000” then ‘or’ in1 and in2 and set the result to out2 — You can assume the width is 4 he and if neither true, set out2 to in1 when “01” => — REGION 4: Write code below –- –multiply: store high bits in out2 and low bits in out1. keep in mind, the width generic –will always be even (no need to account for an extra bit on out out1 or out2) when “10” => — REGION 5: Write code below –- –create the last when statement that accounts for all other cases and set out1 to 0 — REGION 6: Write code below — end case; end process;end BHV;
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