Parallel_Systems_5c M.E.Lock The context for this question is the same as the previous question. 5. Consider the ticket lock algorithm from lecture 4 (slide 108): c. [1.5 points] What are the downsides of the ticket lock algorithm for systems with write-invalidate cache coherence? Briefly explain your answer.

Parallel_Systems_6 Barriers 6. [4 points] Given the following picture of the dissemination algorithm, focusing on node P4, what information does P4 know at the end of round 1?  Explain your answer. 

Virtualization_2 Full Virtualization 2. [4 points] In a fully virtualized environment, consider the following:  Two VMs are currently running. VM1 has 3 processes running; VM2 has 4 processes running.    Assume the size of the hardware page table is 1 MB.    What is the total memory overhead incurred by the Hypervisor for the above configuration? Show your work for any credit.

Parallel_Systems_1 Shared Memory Machines 1. [2 points] Consider a NCC-NUMA architecture for a shared address space multiprocessor.  What guarantees are needed from the architecture to ensure that it provides sequential consistency memory model to the programmer?

OS_Structure_2d Microkernel   The context for this question is the same as the previous question. 2. You are evaluating a microkernel-based OS following the principles of the L3 microkernel. The processor architecture on which this OS is running has the following features:   A byte-addressable 32-bit hardware address space.  Paged virtual memory system with a processor register called PTBR that points to the page table in memory to enable hardware address translation.  A TLB which DOES NOT support Address space IDs. A pair of hardware-enforced segment registers (lower and upper bound of virtual addresses) which limit the virtual address space that can be accessed by a process running on the processor. The use of segment registers can be toggled on or off by the user.  A virtually-indexed physically-tagged processor cache.   d. [2 points] (Answer True/False with justification)  Since the TLB does not support address space IDs, the TLB will always need to be flushed upon a context switch from one protection domain to another. 

Parallel_Systems_9b Parallel System Scheduling The context for this question is the same as the previous question. 9. Consider a multi-threaded multicore CPU is one which each chip has multiple cores, and each core has multiple hardware threads.  The OS chooses the set of application threads to be scheduled on the hardware threads in each core.  Given that the hardware threads share a single processor pipeline on the core,   b. [4 points] What should the OS do ensure that processor pipeline is utilized well?  Why?  

Calculate the CFFA in Yr 1 and Yr 2.  

Calculate the CFFA in Yr 5.  

Which of the following is TRUE about IRR of a project? I.    The IRR rule does NOT account for the risk of the cash flows. II.  When the cash flows change sign more than once, there is always only one IRR.

What would be the charge on an atom of Ni which only has 25 electrons?  [sign][magnitude]