How many total flip-flops will be synthesized for the follow…
How many total flip-flops will be synthesized for the following module? module bad_registers ( input logic clk, input logic rst, input logic [3:0] in_data, output logic [3:0] out_data); logic [3:0] temp1, temp2; always @(posedge clk) begin if (rst) temp1 = 4’b0000; else begin temp1 = in_data + 1; temp2 = temp1 ^ 4’b1010; out_data = temp2 & 4’b1100; end endendmodule
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