L3 Micrоkernel The cоntext fоr this question is the sаme аs the previous question. You аre the Lead Systems Architect for FlashTrade, a High Frequency Trading (HFT) firm. You are designing a specialized OS kernel on top of L3 microkernel to host four client trading algorithms on a single server while ensuring strict proprietary data isolation. The processor architecture you are targeting has the following features: A 32-bit hardware address space. Paged virtual memory system (8KB pages) with a processor register called PTBR that points to the page table in memory. A Tagged TLB supports tagging entries with Address Space IDs (ASIDs). A pair of hardware-enforced segment registers (base and limit) which restrict the virtual address range accessible by a process. A virtually indexed, physically tagged processor cache. Your system runs a shared Kernel Lib (K), which requires 512 MB, and four client protection domains. Each client runs as a user level process. The clients use services provided by the Kernel Lib (libraries for network access, memory management, and CPU scheduling). You design the hardware address spaces for each client as follows: Client A: Kernel Lib (512 MB) + Trading Model (2.5 GB) Client B: Kernel Lib (512 MB) + Trading Model (2.5 GB) Client C: Kernel Lib (512 MB) + Trading Model (1.5 GB) + Forecast Model (1.5 GB) Client D: Kernel Lib (512 MB) + Trading Model (3 GB) e) [2 points] Answer True/False with justification. No credit without justification. The design guarantees that the clients are protected from the Kernel.