GradePack

    • Home
    • Blog
Skip to content
bg
bg
bg
bg

GradePack

After In re Gault (1967) Supreme Court declares Juveniles ha…

After In re Gault (1967) Supreme Court declares Juveniles have the right to counsel, to confront and examine accusers.

Read Details

In the figure, INV1 drives three other inverters via an inte…

In the figure, INV1 drives three other inverters via an interconnect with parameters R2=R1; R3=3R1; R4=5R1; C2=C3=C4=C1. The delay between points A and B is 150 ps. Determine the delay between points A and B if C4 is tripled and R4 and R1 is halved. Use Elmore’s delay formula and ignore all inverter delays (assume they are very fast).  ELMORE-UPSCALED.jpg

Read Details

H-tree configuration is useful and allows late design change…

H-tree configuration is useful and allows late design changes, since clock is easily accessible at various points on the die.

Read Details

MULTIPLE ANSWER PROBLEM:  Determine inverter tapering size A…

MULTIPLE ANSWER PROBLEM:  Determine inverter tapering size A, and Dynamic power dissipation P of 3rd inverter. Figure shows the inverter string design in a 0.6 micron 3.3 V CMOS technology. To optimize for the delay, each inverter is made A times larger than the previous inverter stage. Assume that the input and output capacitance of the first inverter (before the second stage connected) is given as 12 fF and 5 fF, respectively. Also, take the load capacitance Cload as 36,000 fF. The number of stages N calculated to be 8. Determine the tapering size A Determine the dynamic power dissipation of the 3rd inverter at a switching frequency of 1 GHz.  For this you need to calculate the total load capacitance at the output of 3rd inverter and then use dynamic power formula P= CLVDD2f Choose the values closest to what you have found. Assume minimum size inverter has Rn=12k/sq, Rp=36k/sq (in case you need it).   buffer-UPSCALED.jpg

Read Details

NMOS Inverter with Depletion Load configuration has the disa…

NMOS Inverter with Depletion Load configuration has the disadvantage that the output logic high value is not a full VDD, rather it is a reduced one..

Read Details

Clock Jitter is the Maximum difference of the clock arrival…

Clock Jitter is the Maximum difference of the clock arrival times to the inputs of flip-flops.

Read Details

frequency-upscaled.jpg Choose the answer closest to what you…

frequency-upscaled.jpg Choose the answer closest to what you have found!

Read Details

We want to detect S-A-0 (Stuck at zero) fault at node h.   W…

We want to detect S-A-0 (Stuck at zero) fault at node h.   Which of the following vector can detect this error? sa0-UPSCALED.jpg

Read Details

Problem:  Use the figure below to answer the following quest…

Problem:  Use the figure below to answer the following questions.  Assume the assembly rotates about the z-axis at 12 rad/s while the disk rotates about the y-axis at 10 rad/s. The mass of the disk is 0.5 slugs. LO 21a & 21b: What is the mass moment of inertia of the disk about the y- and the z-axes?  Show your work. Value Solution Units [sol] [units] [sol2] [units2]

Read Details

Problem:  Use the figure below to answer the following quest…

Problem:  Use the figure below to answer the following questions.  Assume the assembly rotates about the z-axis at 12 rad/s while the disk rotates about the y-axis at 10 rad/s. The mass of the disk is 0.5 slugs. LO 21a: What is the total kinetic energy of the disk? Show your work. Solution Units [sol] [units]

Read Details

Posts pagination

Newer posts 1 … 29,531 29,532 29,533 29,534 29,535 … 82,081 Older posts

GradePack

  • Privacy Policy
  • Terms of Service
Top