Problem 1: Short Questions (24 pts) 1.1 Please select True o…
Problem 1: Short Questions (24 pts) 1.1 Please select True or False for the following statements. (8 pts) (True / False) a. DIBL effect leads to lower device leakage. (True / False) b. A 7nm FinFET transistor has its gate length at 7nm. (True / False) c. At the same length, metal-1 has a lower resistance and capacitance than metal-3. (True / False) d. Hold time violations are easier to fix than setup time violations after a chip is fabricated. (True / False) e. Fin width (FinFET) is a design parameter that a circuit designer decides as she wishes. (True / False) f. DRC rules are defined by the EDA tool vendors, such as Cadence. (True / False) g. Carry out bit is often on the critical path of a 1-bit full adder. (True / False) h. Clock skew is the difference in arrival times between the launch flip-flop clock edge and the capture flip-flop clock edge. [Write down your answers on your solution papers. No explanation is needed.]
Read DetailsProblem 2: Time-borrowing (10pts) Assume tCLK2Q = 55ps; tD2…
Problem 2: Time-borrowing (10pts) Assume tCLK2Q = 55ps; tD2Q = 100ps; tSETUP = 35ps; tHOLD = 0ps for both latches and flip-flops. For the following path to run without any timing violation, determine the maximum clock frequency it can run at. Show how you arrive at your answers. For logic delay between flip-flops and/or latches, use the following values: A = 655ps, B = 100ps, C = 300ps, D = 450ps, E = 300ps. [Write down and show how you get the answers on your solution papers.]
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