Bоnus (wоrth less pоints аnd grаded more criticаlly, because it is a bonus) In this Bonus you will write a testbench named RAtest to test this Ripple adder // 4 bit inputs A, B, and 1 bit input Cin (carry in), // these inputs are added by the ripple adder // output 4 bit Sum of input, 1 bit Cout (carry out) // and overflow OF module RA (input [3:0] A, B, input Cin, output reg [3:0] Sum, output Cout, OF); ... you don't have to fill this in and won't get credit for filling it in if you do endmodule Write in your testbench in Verilog or System Verilog and add AA = 4’b0110 and BB = 4’b0011 and Cin = 1’b1 using the ripple adder described above. The testbench should have have an initial statement, instantiation, and delays. If you use System Verilog clearly state you are using it for credit. Within these constraints and our coding standard use the minimum number of lines. Display all results (Sum, Cout, OF) to the screen using a $display statement (there is an example in the cheat sheet). Write your code with good organization. If you have procedural blocks indent them for full credit. Your answer must be complete, succinct, and clear and with no compile, simulation, or synthesis errors. Also, What should the resulting value of Sum, Cout, and OF in this case be? Is Sum correct?