Consider the following 5-stage pipeline with the provided per stage delay. What is the maximum frequency this pipeline can be clocked at in MHz? (1 MHz = 106 Hz; 1 ns = 10-9 s; 1 Hz = 1 clock cycle/s) Give your answer as a whole number without units. [q1]   Sean decides to modify this pipeline by combining the ID/RR and EX stages. The new per stage delay will be the sum of the per stage delays of the 2 combined stages. What will the pipeline’s new frequency be in MHz? Give your answer as a whole number in MHz without units. [q2]

What is the index?

What is the offset (in binary) of the given cache address?

Leave any assumptions you may have below.

The 32-bit LC-2200 instruction set defines 4 different instruction types. Each type allocates the bits for different purposes. For an I-type instruction, select the following fields that appear in that instruction.

The memory manager selects page B using a page replacement algorithm. What algorithm is this using for page replacement?

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